The present invention relates to semiconductor devices, and, more particularly, to cleaning processes to control contamination from metal comprising gate electrodes and fabrication methods for integrated circuits (ICs).
Conventional methods of creating CMOS devices use gate electrodes comprising polysilicon that is deposited and patterned over a layer of silicon oxide or silicon oxynitride (SiON). Recently, the polysilicon gate electrode has been replaced by a metal comprising gate electrode. As known in the art, the use of a metal as the gate electrode avoids charge depletion in semiconductor comprising electrodes such as polysilicon that limits the effective scaling of the gate electrical thickness.
Gate electrode formation occurs fairly early in the process flow. This early portion of the process flow has historically been without any metal comprising layers. Having all non-metal comprising layers generally allows the same tool to be used for a wide variety of processing steps, without any processing restrictions. However, the introduction of metal comprising gate electrode materials has complicated this situation due to the need to have separate processing tools for processing wafers having metal comprising layers and wafers having all non-metal comprising layers to avoid or at least limit metallic cross-contamination. Dedicated processing tools for wafers having non-metal comprising layers and wafers having metal comprising layers increases final die costs by requiring more processing tools and an increase in required floor space for the added tools.